[Libre-soc-bugs] [Bug 716] PartitionedSignal Slice and Part needed for __getitem__

bugzilla-daemon at libre-soc.org bugzilla-daemon at libre-soc.org
Sat Oct 16 12:52:35 BST 2021


--- Comment #13 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Jacob Lifshay from comment #12)
> (In reply to Luke Kenneth Casson Leighton from comment #8)
> > well, one way to find out: try it :)  comb assignments should
> > (LHS or RHS) result in netlist merging, so i believe with a say... 40%
> > certainty it should work :]
> I'm 99% certain that won't work, since yosys tries to emulate verilog's
> semantics, and the following doesn't work in verilog:
> wire a, b, c;
> # this doesn't connect a with c
> always b = a;
> always b = c;

so you didn't check it, with a simple test comprising 15-20 lines,
before writing nearly 400 and introducing new classes and concepts
that haven't been demonstrated to be needed.

you keep doing this.

now please can you do what was asked, which was to write a simple test.

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