[Libre-soc-bugs] [Bug 716] PartitionedSignal Slice and Part needed for __getitem__

bugzilla-daemon at libre-soc.org bugzilla-daemon at libre-soc.org
Sat Oct 16 02:33:23 BST 2021


--- Comment #12 from Jacob Lifshay <programmerjake at gmail.com> ---
(In reply to Luke Kenneth Casson Leighton from comment #8)
> well, one way to find out: try it :)  comb assignments should
> (LHS or RHS) result in netlist merging, so i believe with a say... 40%
> certainty it should work :]

I'm 99% certain that won't work, since yosys tries to emulate verilog's
semantics, and the following doesn't work in verilog:
wire a, b, c;

# this doesn't connect a with c
always b = a;
always b = c;

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