[Libre-soc-bugs] [Bug 716] PartitionedSignal Slice and Part needed for __getitem__

bugzilla-daemon at libre-soc.org bugzilla-daemon at libre-soc.org
Fri Oct 15 22:00:44 BST 2021


--- Comment #8 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Jacob Lifshay from comment #4)

> I think you're missing my point, which is that, for the following code:
> a = SimdSignal(...)
> b = SimdSignal(...)
> c = Cat(a, b)
> d = a[5]
> m.d.comb += [c.eq(0), d.eq(0)]
> c and d are the lhs of an assignment, which means that the signals *have to
> flow backwards* from c and d back to a and b.
> From reading the existing source for PartitionedCat, PartitionedAssign, and
> SimdSignal, that case isn't handled at all (unless I'm missing something).

well, one way to find out: try it :)  comb assignments should
(LHS or RHS) result in netlist merging, so i believe with a say... 40%
certainty it should work :]

it's not intuitively obvious, i appreciate, and early versions of
nmigen sim couldn't handle long assignment chains (whoops)

You are receiving this mail because:
You are on the CC list for the bug.

More information about the libre-soc-bugs mailing list