[Libre-soc-bugs] [Bug 716] PartitionedSignal Slice and Part needed for __getitem__

bugzilla-daemon at libre-soc.org bugzilla-daemon at libre-soc.org
Fri Oct 15 21:06:09 BST 2021


--- Comment #7 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Jacob Lifshay from comment #5)

> That operators need to return SimdSignals is totally obvious to me...

:)  the non-obvious bit is, "but... butbut... is that it??" :)

> actually, now that I think about it, Slice and Cat and Part have to return a
> SimdValue, not a SimdSignal, since otherwise a[5].eq(b) will assign to the
> signal that is a result of slicing, but the assignment won't propagate back
> to `a` since it won't know where to propagate to.

oo, oo, err... i need to think about that one.  this was part of the
mind-bending involving Assign.

... half-a-brainwave: i think it's ok... as long as the submodules entirely
use the comb domain (which they do), the netlist from LHS and RHS become
synonymous in effect, with the end result that an eq assignment should

(this because unlike programming variables where assignment to LHS
overwrites RHS but a second assignment preserves the first, HDL comb
eq()s make the LHS and RHS "the same netlist")

i will have to think about that, or simply try a test Cat(x, y).eq(z)
which is doable because Cat and Assign are available.

ooo, it'd better work!

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