[Libre-soc-bugs] [Bug 716] PartitionedSignal Slice and Part needed for __getitem__

bugzilla-daemon at libre-soc.org bugzilla-daemon at libre-soc.org
Fri Oct 15 09:00:18 BST 2021


https://bugs.libre-soc.org/show_bug.cgi?id=716

--- Comment #4 from Jacob Lifshay <programmerjake at gmail.com> ---
(In reply to Luke Kenneth Casson Leighton from comment #3)
> (In reply to Jacob Lifshay from comment #2)
> > I think we also need something to handle stuff like:
> > a[3:5].eq(b)
> > since assigning to a slice is quite common.
> 
> this should work automatically because (i forgot to
> emphasise) the return result from the submodule
> (which is then a return result of SimdSignal.Slice/Part,
> which in turn is then a return result of Value.__getitem__)
> must be *another SimdSignal*.

I think you're missing my point, which is that, for the following code:
a = SimdSignal(...)
b = SimdSignal(...)
c = Cat(a, b)
d = a[5]
m.d.comb += [c.eq(0), d.eq(0)]

c and d are the lhs of an assignment, which means that the signals *have to
flow backwards* from c and d back to a and b.

>From reading the existing source for PartitionedCat, PartitionedAssign, and
SimdSignal, that case isn't handled at all (unless I'm missing something).

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