[Libre-soc-bugs] [Bug 716] PartitionedSignal Slice and Part needed for __getitem__

bugzilla-daemon at libre-soc.org bugzilla-daemon at libre-soc.org
Fri Oct 15 08:22:06 BST 2021


--- Comment #3 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Jacob Lifshay from comment #2)
> I think we also need something to handle stuff like:
> a[3:5].eq(b)
> since assigning to a slice is quite common.

this should work automatically because (i forgot to
emphasise) the return result from the submodule
(which is then a return result of SimdSignal.Slice/Part,
which in turn is then a return result of Value.__getitem__)
must be *another SimdSignal*.

that's very important.

have a close look at repl.py and prepl.py for how it
(very surprisingly) works.

the submodule is responsible for computing the width
of the output SimdSignal.  in the case of repl.py it
was dead easy, take the width of the input and multiply
it by the count.  cat.py likewise, just sum up the
total width of all input args.

for Slice and Part the width is easily calculated (statically)
thank goodness by analysing the slice which only
takes integers/Consts so can also be done in
the constructor.

in early revisions Michael and i forgot to make
the submodule return result a SimdSignal, we accidentally
returned a Signal().  if that mistake had not been
corrected then yes, things like Cat(simd11, simd2).eq(simd3)
would totally fail.

even things like simd1+simd2+simd3 would totally fail
because the first add would have returned a Signal
not another SimdSignal, and the 2nd add of simd3
would have produced utterly the wrong result.

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