[Libre-soc-bugs] [Bug 550] binutils support needed for svp64

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=550

--- Comment #30 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Luke Kenneth Casson Leighton from comment #29)

> it could well be covered entirely by a single 64 bit uint64_t
> per row, comprising the ORing of a series of #defines:
> not even a struct need be created (unlike in the VHDL case).

... possibly.  there's actually quite a lot.  looking at the VHDL:

        -- insn  Ptype  Etype  in1  in2  in3  out  out2  CR in  CR out  sv_in1 
sv_in2  sv_in3  sv_out  sv_out2  sv_cr_in  sv_cr_out
2#0100001010# => (P1, EXTRA3, RA, RB, NONE, RT, NONE, NONE, CR0, Idx1, Idx2,
NONE, Idx0, NONE, NONE, Idx0), -- add

so:

* sv_* fields are all 3-bit (5 possible values):  (None, Idx0, Idx1, Idx2,
Idx3)
* there are 7 of those (in1, in2, in3, out, out2, cr_in, cr_out)
* that totals 21 bits
* Ptype (predicate type) is 1 bit: PTYPE_P1 or PTYPE_P2
* Etype (EXTRA fields type) is 1 bit: EXTRA2 or EXTRA3

(total 23 so far)

but, ahh, where there is sv_in1 .... etc. there are also 7 fields
in1, in2, in3, out, out2, CRin, Crout which tell you *which register*
those 7 sv_* fields are associated with.  in the example above:

* in1 = RA, but sv_in1 = Idx1.  therefore:
  - RA is an input
  - RA EXTRA3 encoding is in position Idx1
* in2 = RB, but sv_in2 = Idx2 therefore:
  - RB is an input
  - RB EXTRA3 encoding is in position Idx2
...
* CRout = CR0, but sv_cr_out = Idx0.  therfore
  - CR0 is an **OUTPUT**
  - CR0 EXTRA3 encoding is in position Idx0

now, the number of possible entries for in1/in2 etc. is:

* RA
* RB
* RC
* RT
* EA
* FRA
* FRB
* FRC
* FRS
* FRT
* CR0
* CR1

so 12 possible values, requiring 4 bits.  there are 7 of them,
therefore another 4*7=28 bits

28 + 23 == 51

ooooo it's still achievable to fit into all the SVP64 table
encoding information into a single uint64_t

-- 
You are receiving this mail because:
You are on the CC list for the bug.