[Libre-soc-bugs] [Bug 50] nmigen pinmux

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=50

--- Comment #35 from andrey at technepisteme.xyz ---
(In reply to Luke Kenneth Casson Leighton from comment #34)
> nggggh i just realised: enumeration of the pad ports was masking the
> actual inputs/outputs
> 
>     def get_input(self, pin, port, attrs, invert):
>         (res, pin, port, attrs) = self.padlookup[pin.name]
> 
> should have been:
> 
>     def get_input(self, pin, port, attrs, invert):
>         (padres, padpin, padport, padattrs) = self.padlookup[pin.name]
> 
> ngggggh.  there are *six* pieces of information to wire up.

After your explanation about ports here:
https://libre-soc.org/irclog/%23libre-soc.2021-11-16.log.html
I added the changes to get_input_output(). The code runs, and the yosys diagram
is quite a bit more complex...
https://git.libre-soc.org/?p=pinmux.git;a=blob;f=src/spec/testing_stage1.py;h=f7dc99ca31f912cb0d82c43d769f6db229412873;hb=c49e5c233611122bd5838ba02f255801371c235f#330

Here's the combinatorial code (it looks woozy, but actually quite managable):
# Create aliases for the port sub-signals
port_i = port.io[0]
port_o = port.io[1]
port_oe = port.io[2]
padport_i = padport.io[0]
padport_o = padport.io[1]
padport_oe = padport.io[2]

# Connect SoC pins to SoC port
m.d.comb += pin.i.eq(port_i)
m.d.comb += port_o.eq(pin.o)
m.d.comb += port_oe.eq(pin.oe)
# Connect SoC port to JTAG io.core side 
m.d.comb += port_i.eq(io.core.i)
m.d.comb += io.core.o.eq(port_o)
m.d.comb += io.core.oe.eq(port_oe)
# Connect JTAG io.pad side to pad port
m.d.comb += io.pad.i.eq(padport_i)
m.d.comb += padport_o.eq(io.pad.o)
m.d.comb += padport_oe.eq(io.pad.oe)
# Connect pad port to pad pins
m.d.comb += padport_i.eq(padpin.i)
m.d.comb += padpin.o.eq(padport_o)
m.d.comb += padpin.oe.eq(padport_oe)

Can you confirm this is the behaviour we need Luke?

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