[Libre-soc-bugs] [Bug 50] nmigen pinmux

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=50

--- Comment #32 from andrey at technepisteme.xyz ---
(In reply to Luke Kenneth Casson Leighton from comment #31)
> (In reply to andrey from comment #30)
> 
> i just realised though, that returning $tristate has to go.  $tristate
> is exactly the same as if this was a single FPGA endpoint. that is precisely
> and exactly what we do not want.
Sure.

> 
> now, in some distant future version we might actually want to output
> $IOcell from C4M FlexLib IO package, but not right now, because it is
> coriolis2 that is taking care of the IOPad cell allocation, and for
> that to work, it has to have the triple signals: i, o and oe.
Makes sense.

I made a naive modification, connecting the pin.i/o/oe straight to port.i/o/oe
(or through the JTAG block):
https://git.libre-soc.org/?p=pinmux.git;a=blob;f=src/spec/testing_stage1.py;h=7654d177756ae48db4ccf1735f27d735b8341d2d;hb=e4b662d5723dd919ef3c5d1f18c92395e63168dd#l280
"""
if pin.name in ['clk_0', 'rst_0']: # sigh
    print("No JTAG chain in-between")
    # Can port's i/o/oe be accessed like this?
    m.d.comb += port.o.eq(pin.o)
    m.d.comb += port.oe.eq(pin.oe)
    m.d.comb += pin.i.eq(port.i)
    return m
(res, pin, port, attrs) = self.padlookup[pin.name]
io = self.jtag.ios[pin.name]
m.d.comb += io.core.o.eq(pin.o)
m.d.comb += io.core.oe.eq(pin.oe)
m.d.comb += pin.i.eq(io.core.i)
m.d.comb += io.pad.i.eq(port.i)
m.d.comb += port.o.eq(io.pad.o)
m.d.comb += port.oe.eq(io.pad.oe)
"""

However, I'm getting an AttributeError about a missing "i" signal:
Traceback (most recent call last):
  File "testing_stage1.py", line 353, in <module>
    p.build(top)
  File "/home/rohdo/work/nmigen/nmigen/build/plat.py", line 95, in build
    plan = self.prepare(elaboratable, name, **kwargs)
  File "/home/rohdo/work/nmigen/nmigen/build/plat.py", line 152, in prepare
    add_pin_fragment(pin, self.get_tristate(pin, port, attrs, invert))
  File "testing_stage1.py", line 300, in get_tristate
    m.d.comb += pin.i.eq(io.core.i)
  File "/home/rohdo/work/nmigen/nmigen/hdl/rec.py", line 146, in __getattr__
    return self[name]
  File "/home/rohdo/work/nmigen/nmigen/hdl/rec.py", line 158, in __getitem__
    .format(reference, item, ", ".join(self.fields))) from None
AttributeError: Record 'gpio_0__gpio0__oe' does not have a field 'i'. Did you
mean one of: o, oe?

Not sure of how to access the port's i,o,oe signals. Looks like there are only
"i" OR "o/oe" gpios types only, I guess something hasn't been configured
beforehand?

-- 
You are receiving this mail because:
You are on the CC list for the bug.