[Libre-soc-bugs] [Bug 50] nmigen pinmux

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=50

--- Comment #31 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to andrey from comment #30)

> See the new diagram I drew up based on the topology from nmigen's plat.py
> https://libre-soc.org/docs/pinmux/

briilliant. 

> (The I/O and tristate statements were made from it, I recommend checking it
> for your sanity ;) )

:)

> From what I can tell it works, but I'll need further confirmation from Luke
> to make sure this is heading in the right direction.

yeah looks great.

i just realised though, that returning $tristate has to go.  $tristate
is exactly the same as if this was a single FPGA endpoint. that is precisely
and exactly what we do not want.

now, in some distant future version we might actually want to output
$IOcell from C4M FlexLib IO package, but not right now, because it is
coriolis2 that is taking care of the IOPad cell allocation, and for
that to work, it has to have the triple signals: i, o and oe.

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