[Libre-soc-bugs] [Bug 739] NGI POINTER Gigabit Router Pinout Considerations

bugzilla-daemon at libre-soc.org bugzilla-daemon at libre-soc.org
Mon Nov 15 21:05:17 GMT 2021


--- Comment #16 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Jean-Paul.Chaput from comment #15)

>   OK. I get the idea. One more question regarding the various clocks:
>   how widespread are they *in* the design?

not at all.  if more than 1,000 transistors there is something very wrong.
(the exception being JTAG CLK but even there it can run at only 5khz or
gosh, maybe 1 mhz).

the external clocks are usually one side of a Clock-Domain-Crossing
FF or FIFO Synchroniser.  this will be for 4, 8 bit or 32 bit IO data
so it does actually need to be balanced timing on the FFs.

there is also a *little* bit of logic, usually things like "is this
ready to send" and so on.  for JTAG the entire Shift Registers are
driven by JTAG TCK and there are a lot of single bit FFs in a chain
there, with quite a few CDC Synchronisers too.

mostly, though, the PHYs work hard to get the data crossed over to
"main system clock" as quickly as possible.

>   I mean, making a whole
>   H-Tree across *all* the area if only a very specific part is
>   concerned would be a waste.

definitely.  more than that, these are the numbers:

* five RGMII clocks 2.5/25/125 mhz
* two ULPI clocks 60 mhz
* one JTAG TCK 5khz to 1mhx
* one I2C CLK 400 mhz max (hm we need pullup and Open Drain for that)
* one SPI which can go up to 25 mgz
* one for SDRAM, up to 133 mhz

each of these will have extremely local PHY logic, easily identifiable
by module.  except JTAG which might get a bit liberally distributed

>   We may want to either create a
>   sub-block with its localized H-Tree, or develop a specific
>   ad-hoc buffering version for one clock.

adhoc sounds like a fantastic idea for RGMII ULPI SPI and I2C, it
would not interfere as trees 

one potential problem as trees is, there may be too many to manage
in one area because of pin layout.

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