[Libre-soc-bugs] [Bug 50] nmigen pinmux

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=50

--- Comment #21 from andrey at technepisteme.xyz ---
(In reply to Luke Kenneth Casson Leighton from comment #20)
> okaay things are getting hairy but functional.  first observation/lesson:
> under no circumstances declare a pin as "io" type.  this is reserved for
> single wires that are bi-directional.
> 
> instwad, sigh, io pins have to be declared as a triple of wires: i, o and
> oe as *actual* three-wire Resources().
> 
> second: the autogenerated names for the pads, ending up as top-level
> Signals in the verilog output, are awful :)  but, this can be investigated
> later.
> 
> i did phase 2 already, it works great, and can be tested/integrated
> later.
> 
> which means moving to phase 3 already.
> 
> andrey you will need to install c4m-jtag for this part of the
> experiment, and we will need a cut/pasting a copy of jtag.py
> https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/debug/jtag.py;hb=HEAD
> 
> use the libresoc c4m-jtag it has DMI in it.
Installed nmigen-soc and c4m-jtag from libre-soc.

The latest testing_stage1.py runs with no issues.

Not sure how to convert to IL for visualisation with Yosys.
Tried copying code from jtag.py:
vl = rtlil.convert(dut)
with open("test_jtag.il", "w") as f:
        f.write(vl)

but dut replaced with DummyPlatform in my case.
Got errors about DummyPlatform not being elaborateble (probably because
DummyPlatform by itself is not an HDL module, right?)

-- 
You are receiving this mail because:
You are on the CC list for the bug.