[Libre-soc-bugs] [Bug 50] nmigen pinmux

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=50

--- Comment #20 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
okaay things are getting hairy but functional.  first observation/lesson:
under no circumstances declare a pin as "io" type.  this is reserved for
single wires that are bi-directional.

instwad, sigh, io pins have to be declared as a triple of wires: i, o and
oe as *actual* three-wire Resources().

second: the autogenerated names for the pads, ending up as top-level
Signals in the verilog output, are awful :)  but, this can be investigated
later.

i did phase 2 already, it works great, and can be tested/integrated
later.

which means moving to phase 3 already.

andrey you will need to install c4m-jtag for this part of the
experiment, and we will need a cut/pasting a copy of jtag.py
https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/debug/jtag.py;hb=HEAD

use the libresoc c4m-jtag it has DMI in it.

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