[Libre-soc-bugs] [Bug 50] nmigen pinmux

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=50

--- Comment #6 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
platform files such as this:

https://github.com/nmigen/nmigen-boards/blob/master/nmigen_boards/arty_a7.py

class _ArtyA7Platform(Xilinx7SeriesPlatform):
    package     = "csg324"
    speed       = "1L"
    default_clk = "clk100"
    default_rst = "rst"
    resources   = [
        Resource("clk100", 0, Pins("E3", dir="i"),
                 Clock(100e6), Attrs(IOSTANDARD="LVCMOS33")),
        Resource("rst", 0, PinsN("C2", dir="i"), Attrs(IOSTANDARD="LVCMOS33")),
        *LEDResources(pins="H5 J5 T9 T10", attrs=Attrs(IOSTANDARD="LVCMOS33")),
        RGBLEDResource(0, r="G6", g="F6", b="E1", 
                       attrs=Attrs(IOSTANDARD="LVCMOS33")),

would become:

class NGIPointerPlatform(DynamicASICPlatform):
     ....

where DynamicASICPlatform would, instead of explicitly adding
resources one by one, do this:

txt = open(JSON_FILE_WITH_PINSPECS).readlines()

for line in txt:
     if line.resourcename == 'JTAG':
           resources.append(JTAGResource("jtag", 0, Pins(line.tck/tms/tdi/tdo)

etc. etc.

again this is very straightforward.

where it will get complicated is how the hell to add JTAG Boundary Scan.
for litex, a *duplicate* ResourceManager was required.

https://git.libre-soc.org/?p=nmigen.git;a=blob;f=nmigen/build/res.py;h=fde981fcf3ad4b7427de8ac9ee2c62a1598721f0;hb=e88d283ed30448ed5fe3ba264e3e56b48f2a4982#l17

* one ResourceManager is for the actual inputs/outputs. it connects between:
  - ASIC corona (actual IOpads)
  - JTAG
* one ResourceManager is for the actual peripherals.  it connects between:
  - the peripheral(s) - UART, I2C, SPI, SDRAM
  - JTAG

PlatformManager *derives* from ResourceManager already, so that is one
covered:

https://git.libre-soc.org/?p=nmigen.git;a=blob;f=nmigen/build/plat.py;h=c1d8fc693c0c180d56f319433889b10125ee573e;hb=e88d283ed30448ed5fe3ba264e3e56b48f2a4982#l21

however to "redirect", it may.... sigh... be necessary for the
DynamicASICPlatform to override get_input, get_output etc. etc.

https://git.libre-soc.org/?p=nmigen.git;a=blob;f=nmigen/vendor/xilinx.py;h=f332a93230fd3c853e93322f6c11207e0181d94b;hb=e88d283ed30448ed5fe3ba264e3e56b48f2a4982

this can be done with a Mix-In class because, sigh, FPGA testing of
JTAG Boundary Scan is also necessary.

(and, this would also, in some future version, be the place where
the GPIO mux redirection also is added, re-mapping / redirecting
from one-to-many and many-to-one - many peripheral pins to one IO pin)

the DynamicASICPlatform would in no way be as complicated as
Vivado etc. etc.  in fact most of the code is deleted.  the actual
platform should end up as trivial as this:

https://git.libre-soc.org/?p=libresoc-litex.git;a=blob;f=libresoc/ls180.py;h=81858edd9ad026ae05187ed6c48d318a7fe60647;hb=b55917aafa6bbc9f16e1d97dc095e929c31aa81a#l171

def build - outputs verilog.

aside from the add_input, add_output etc. etc. overrides which will
redirect to the Corona Platform Resource:

    def get_input(self, pin, port, attrs, invert):
        self._check_feature("single-ended input", pin, attrs,
                            valid_xdrs=(0,), valid_attrs=None)

        m = Module()
        m.d.comb += pin.i.eq(self._invert_if(invert, port))
        return m

becomes:


    def get_input(self, pin, port, attrs, invert):
        self._check_feature("single-ended input", pin, attrs,
                            valid_xdrs=(0,), valid_attrs=None)

        m = Module()
        corona_pin = self.get_corona_pin(pin, port, attrs, invert)
        jtag_in = self.jtag.get_core_side(pi, port, attrs, invert)
        jtag_out = self.jtag.get_core_side(pi, port, attrs, invert)

        # instead of this:
        # m.d.comb += pin.i.eq(self._invert_if(invert, port))
        # put JTAG in the middle:

        m.d.comb += jtag_out.eq(self._invert_if(invert, port))
        m.d.comb += pin.i.eq(jtag_out)

        return m

likewise for output, and etc. etc. etc. etc.

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