[Libre-soc-bugs] [Bug 50] nmigen pinmux

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=50

--- Comment #5 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Luke Kenneth Casson Leighton from comment #4)
> https://github.com/ktemkin/lambdasoc/blob/master/examples/sram_soc.py
> 
> this is what needs autogenerating.
> 
> instead of explicit instances of sram, serial, etc, pinmux enumeration
> creates pinsets, instantiates the peripheral and adds it, on-demand.

this:

https://git.libre-soc.org/?p=pinmux.git;a=blob;f=src/spec/i_class.py;hb=HEAD#l63

  63     ps = PinSpec(pinbanks, fixedpins, function_names,
  64                  {'lcd': {'bus': 'fastbus',
  65                           'mmap': [['Cfg', 0x20000, 10]
  66                                    ]},
  67                   'jtag': {'bus': 'fastbus'},
  68                   'fb': {'bus': 'fastbus'},
  69                   'sdr': {'bus': 'fastbus',
  70                           'mmap': [['Mem', 0x70000000, 0x400000],
  71                                    ['Cfg', 0x17000, 12]
  72                                    ]},
  73                   })

turns into this:

        self._arbiter = wishbone.Arbiter(addr_width=30, data_width=32,
                                         granularity=8,
                                         features={"cti", "bte"})
        self._decoder = wishbone.Decoder(addr_width=30, data_width=32,
                                         granularity=8,
                                         features={"cti", "bte"})

        self.cpu = MinervaCPU(reset_address=reset_addr)
        self._arbiter.add(self.cpu.ibus)
        self._arbiter.add(self.cpu.dbus)

        self.rom = SRAMPeripheral(size=rom_size, writable=False)
        self._decoder.add(self.rom.bus, addr=rom_addr)

        self.ram = SRAMPeripheral(size=ram_size)
        self._decoder.add(self.ram.bus, addr=ram_addr)

        self.uart = AsyncSerialPeripheral(divisor=uart_divisor, pins=uart_pins)
        self._decoder.add(self.uart.bus, addr=uart_addr)


it's actually incredibly simple.  once, of course, the underlying
infrastructure is actually there.

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