[Libre-soc-bugs] [Bug 741] bitmanip ALU implementation

bugzilla-daemon at libre-soc.org bugzilla-daemon at libre-soc.org
Fri Nov 12 05:32:08 GMT 2021


--- Comment #14 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Jacob Lifshay from comment #13)
> (In reply to Luke Kenneth Casson Leighton from comment #12)
> > (In reply to Jacob Lifshay from comment #11)
> > > Note that the form I added is called TI (for TernaryI) and the immediate
> > > field is called TII (for TernaryI Immediate).
> > 
> > the convention, created by the microwatt team, and followed in all 75
> > operations, is to use the same microcode op for both immediate and
> > nonimmediate.
> > this is achieved by placing the immediate into the data lanes of the
> > registers
> > whereupon the Function Unit knows nothing at all about immediates and 
> > consequently a designation and naming convention based on immediates
> > is completely inappropriate and misleading.
> here, the name is based on immediate (or not) because the TI form is *only*
> ever used with ternaryi...

please re-read what i wrote, the answer is exactly the same.
because you have not been directly involved in this level
of detail before, you do not understand it (and are not
listening. again).

for the third and final time, i will not say it again:
rename the operation.

regarding pipe_data.py, the 3 src registers need to be called
ra rb and rc because of this code in core.py

 457             # argh.  an experiment to merge RA and RB in the INT regfile
 458             # (we have too many read/write ports)
 459             if self.regreduce_en:
 460                 if regfile == 'INT':
 461                     fuspecs['rabc'] = [fuspecs.pop('rb')]
 462                     fuspecs['rabc'].append(fuspecs.pop('rc'))
 463                     fuspecs['rabc'].append(fuspecs.pop('ra'))

these names are local so have nothing to do with the PowerDecoder2
names, it is a little confusing.

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