[Libre-soc-bugs] [Bug 730] adapt ALU test cases to include expected results

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=730

--- Comment #23 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to vklr at vkten.in from comment #21)
> ---
> What can be done?

this means very simply that the code-generator is outputting
the cr values in the wrong bit-order.

whilst kyle is looking at that, you should always assume
that the simulator is 100% correct, at all times.

therefore, automatically and without needing to ask every
time an assertion is encountered, you should correct the
expected results to match.

this should be an automatic and immediate reaction because,
as i explained in previous comments, we know that the simulator
and HDL match.

         e.crregs[0] = 0x1
         e.crregs[2] = 0x2

kyle, there is a function in SelectableInt which
allows extraction of the value in LSB0 order.
you do not have to write one manually which inverts
the bitorder.

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