[Libre-soc-bugs] [Bug 737] in-order single-issue Power ISA 3.0 core

bugzilla-daemon at libre-soc.org bugzilla-daemon at libre-soc.org
Sun Nov 7 22:51:15 GMT 2021


--- Comment #15 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---

hilariously, there's a severe (catastrophic) bug in python 3.7 which
required a workaround (addition of a setup() function) to prevent
a (catastrophic) coredump by /usr/bin/python3.7 due to a null pointer

ignoring that...


 class FSMDivCoreStage(ControlBase):
     def __init__(self, pspec):
-        super().__init__()
-        self.pspec = pspec
-        self.p.i_data = CoreInputData(pspec)
-        self.n.o_data = CoreOutputData(pspec)
-        self.saved_input_data = CoreInputData(pspec)
+        self.pspec = pspec # store now: used in ispec and ospec
+        super().__init__(stage=self)
+        self.saved_input_data = self.ispec()
         self.empty = Signal(reset=1)
         self.saved_state = DivState(64, name="saved_state")
         self.div_state_next = DivStateNext(64)
         self.div_state_init = DivStateInit(64)
         self.divisor = Signal(unsigned(64))

+    def ispec(self):
+        return CoreInputData(self.pspec)
+    def ospec(self):
+        return CoreOutputData(self.pspec)

... you can see how rather than self.p.i_data and self.n.o_data
being explicitly set, the Stage API is supposed to be used: setting
i_data and o_data is the Stage API's job (inherited by ControlBase).

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