[Libre-soc-bugs] [Bug 737] in-order single-issue Power ISA 3.0 core

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=737

--- Comment #14 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/fu/div/fsm.py;h=1b22ca6f3f145f58e547451f496106e07bcc188d;hb=809cf2faa4450901779045cfaa89e69f70ed9f42#l133

crsar, here is an example of an FSM-based pipeline which is setting the
ready/valid signalling directly, itself.

you need:

* derive from ControlBase
* add p.i_data manually
* add n.o_data manually
* set p.o_ready only when ready to accept input (no stall)
* always accept one data per clock when p.i_valid & p.o_ready is true
* only send on data when n.i_ready is HI
* always set n.o_ready at the exact same time as n.o_data is valid

that's about it. quite easy. generally though it is better to properly
use the API by setting up a completely separate "stage" module which
is passed in to ControlBase.  or, the class to pass in stage=self.

hmm i just realised that the DIV FSM is actually completely ignoring the
Stage API, i will update it.

-- 
You are receiving this mail because:
You are on the CC list for the bug.