[Libre-soc-bugs] [Bug 741] bitmanip ALU implementation

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=741

Luke Kenneth Casson Leighton <lkcl at lkcl.net> changed:

           What    |Removed                     |Added
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                 CC|                            |lkcl at lkcl.net

--- Comment #2 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
no looks good, remember ternary is 4in RT RA RB RC ternaryi 3in RA RB RT
so yes, separate pipeline (all pipelines are created/grouped based on register
profile)

usual trick following how
RB is shared with immediate field is to do the same, drop
TII into DecoderBImm class in powerdecoder2.py
then add TII to InOp2 enum and set RB field in CSV
to TII.

also to save having to create subdecoders of op5 suggest
using 11101----- ie use dashes for ignored bits of field
selector

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