[Libre-soc-bugs] [Bug 737] in-order single-issue Power ISA 3.0 core

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=737

--- Comment #5 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
  96 class ReservationStations(Elaboratable):
 110     def __init__(self, num_rows, maskwid=0, feedback_width=None):
 111         self.num_rows = nr = num_rows
 112         self.feedback_width = feedback_width
 113         self.inpipe = InMuxPipe(nr, self.i_specfn, maskwid)   # fan-in
 114         self.outpipe = MuxOutPipe(nr, self.o_specfn, maskwid) # fan-out
 115 
 116         self.p = self.inpipe.p  # kinda annoying,
 117         self.n = self.outpipe.n # use pipe in/out as this class in/out

 118     def set_alu(self, alu):
 119         srlf.alu, self.pseudoalus = alu, []
 120         for i in range(num_rows):
 121             self.pseudoslus.append(PseudoALU(alu, self.p[i], self.n[i])

class PseudoALU:
    def __init__(self, alu, p, n):
        self.alu = alu
        self.p = p
        self.n = n

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