[Libre-soc-bugs] [Bug 737] in-order single-issue Power ISA 3.0 core

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=737

--- Comment #4 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
continuing the investigation: the MultiCompUnits in soc/fu/compunits.py
need to be concurrent, using ReservationStations.

* ReservationStations needs to be enhanced so that "fake" ALU instances
  are created which connect self.n[i] and self.p[i] into
  self.fakealus[i]

* the "fake" ALUs need to be passed each to MultiCompUnits
  in order to present multiple access points to the same
  underlying pipeline

* also their index muxid has to go into the fake alu

* each "fake" ALU back in compunits.py is given a number
  alu0 alu1 mul0 mul1 mul2 etc to give the impression
  of having multiple concurrent units

* in core.py the selector (enable signal) is masked out
  by FU busy signals to ensure that already-allocated
  Compunits do not try to allocate twice.

therefore there is:

* one actual (real) ALU
* one ReservationStation per ALU
* multiple ReservationStations which are named
* the appearance of more FunctionUnits than actually exists
* but all results are "managed".

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