[Libre-soc-bugs] [Bug 230] Video opcode development and discussion

bugzilla-daemon at libre-soc.org bugzilla-daemon at libre-soc.org
Sun May 30 06:32:53 BST 2021


--- Comment #74 from Jacob Lifshay <programmerjake at gmail.com> ---
(In reply to cand from comment #72)
> MIPS's float moves are raw bitwise, and they have separate conversion
> instructions. RISC-V's float moves are "convert to/from int". Since ppc has
> the same conversions as MIPS, our float moves should be bitwise raw.

Actually, RISC-V has both raw bitwise fpr <-> gpr moves (fmv.d.x and friends)
and converting fpr <-> gpr moves (fcvt.d.lu and friends). I think we should
have both converting moves and bitwise moves, especially because converting is
easily >90% of the fpr <-> gpr moves, so a conversion taking one combined gpr
-> fpr and convert instruction rather than two (gpr -> fpr bitwise move and a
separate fpr -> fpr int -> fp instruction) is better.

The scalar conversion instructions should support u32/u64/i32/i64 <-> f32/f64.
We need at least truncating conversion for fp -> int and roundeven for int ->
fp, though supporting all of roundeven, floor, ceil, and trunc would be better.

fp -> int conversions should convert NaN to 0 and saturate for
+-infinity/too-big-to-fit values -- that's the behavior needed for Rust, Java,
LLVM's fptosi.sat/fptoui.sat intrinsics, and for OpenCL and Direct3D. IDK if
that matches the other OpenPower conversion instructions (it doesn't match on
x86, which makes conversions on x86 take more instructions in many cases).

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