[Libre-soc-bugs] [Bug 642] New: reduce width of input records by sending only required bits of state / data

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=642

            Bug ID: 642
           Summary: reduce width of input records by sending only required
                    bits of state / data
           Product: Libre-SOC's first SoC
           Version: unspecified
          Hardware: PC
                OS: Linux
            Status: CONFIRMED
          Severity: enhancement
          Priority: ---
         Component: Source Code
          Assignee: lkcl at lkcl.net
          Reporter: lkcl at lkcl.net
                CC: libre-soc-bugs at lists.libre-soc.org
   NLnet milestone: ---

example, in ldst input record:

                  ('msr', 64), # TODO: a lot less bits.  only need PR

also in MMU, and other locations: frequently it is only a few bits
that are needed.  strictly speaking, MSR should be subdivided into
its own regfile by "bits"

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