[Libre-soc-bugs] [Bug 469] Create D-cache from microwatt dcache.vhdl

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=469

--- Comment #43 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
an assessment on how to remove one clock cycle latency on response from the
cache srams

http://lists.mailinglist.openpowerfoundation.org/pipermail/openpower-hdl-cores/2021-May/000262.html

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