[Libre-soc-bugs] [Bug 617] add SVP64 predication to TestIssuer

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=617

--- Comment #16 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Cesar Strauss from comment #14)

> TODO:
> * Zeroing single
> * Zeroing twin

ok i've added the basics, it's a bit of a hack, going into
soc/fu/common_output_stage.py and common_input_stage.py
with a single bit of the predicate mask invert-and-ANDed
with the pred-dz or pred-sz mode field, and passed through
to all Satellite Decoders (PowerSubsetDecoder) in core.

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