[Libre-soc-bugs] [Bug 636] exceptions, predication and zeroing masks need to be added to Function Unit context

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=636

--- Comment #11 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
this may need some additional checking, esp. for 3-operand
(and RS)


commit c8dbc9446617f210d06bd796c7ff5a5a026d6c87 (HEAD -> master)
Author: Luke Kenneth Casson Leighton <lkcl at lkcl.net>
Date:   Wed May 5 16:33:48 2021 +0100

    if zeroing is set, put zero into input or output as requested

+Subproject commit 227f39952a4529cea7f5da76c361bf6b650adff3-dirty
diff --git a/src/soc/fu/common_input_stage.py
b/src/soc/fu/common_input_stage.py
index 09a02006..53e023ad 100644
--- a/src/soc/fu/common_input_stage.py
+++ b/src/soc/fu/common_input_stage.py
@@ -31,7 +31,9 @@ class CommonInputStage(PipeModBase):
         else:
             comb += a.eq(self.i.a)

-        comb += self.o.a.eq(a)
+        # SV zeroing on predicate source zeros the input
+        with m.If(~op.sv_pred_sz):
+            comb += self.o.a.eq(a)

         ##### operand B #####

@@ -46,7 +48,9 @@ class CommonInputStage(PipeModBase):
         else:
             comb += b.eq(self.i.b)

-        comb += self.o.b.eq(b)
+        # SV zeroing on predicate source zeros the input
+        with m.If(~op.sv_pred_sz):
+            comb += self.o.b.eq(b)

         ##### carry-in #####

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