[Libre-soc-bugs] [Bug 636] exceptions, predication and zeroing masks need to be added to Function Unit context

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=636

--- Comment #9 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
should be as simple as this:

commit 73165df2e3ed5c33248141f66c8c8f37c2a18235 (HEAD -> master)
Author: Luke Kenneth Casson Leighton <lkcl at lkcl.net>
Date:   Wed May 5 12:51:26 2021 +0100

    add SVP64 RM fields to ALU input record


where the fields to be added are listed in power_svp64_rm.py

sv_input_record_layout = [
        ('sv_pred_sz', 1), # predicate source zeroing
        ('sv_pred_dz', 1), # predicate dest zeroing
        ('sv_saturate', SVP64sat),
        #('sv_RC1', 1),
    ]

-- 
You are receiving this mail because:
You are on the CC list for the bug.