[Libre-soc-bugs] [Bug 450] Create MMU from microwatt mmu.vhdl

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=450

--- Comment #77 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
diff --git a/src/soc/fu/mmu/fsm.py b/src/soc/fu/mmu/fsm.py
index b7ee3d57..8b660b02 100644
--- a/src/soc/fu/mmu/fsm.py
+++ b/src/soc/fu/mmu/fsm.py
@@ -62,6 +62,7 @@ class LoadStore1(PortInterfaceBase):
         m.d.comb += self.d_in.load.eq(0)
         m.d.comb += self.d_in.byte_sel.eq(mask)
         m.d.comb += self.d_in.addr.eq(addr)
+        m.d.comb += self.d_in.nc.eq(1)
         return None

     def set_rd_addr(self, m, addr, mask):
@@ -80,6 +81,7 @@ class LoadStore1(PortInterfaceBase):
         # this is for peripherals.  same thing done in Microwatt
loadstore1.vhdl
         with m.If(addr[28:] == Const(0xc, 4)):
             m.d.comb += self.d_in.nc.eq(1)
+        m.d.comb += self.d_in.nc.eq(1)
         return None #FIXME return value

     def set_wr_data(self, m, data, wen):


when switching off cacheing, litexbios completes its checksum correctly.
this tells us that there's an issue associated with reading a sequential
block of 64k of RAM.

investigating the first few LOADs shows no issue at all.  current dcache
unit tests already go up to 4k words (and pass): clearly this isn't enough.

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