[Libre-soc-bugs] [Bug 469] Create D-cache from microwatt dcache.vhdl

bugzilla-daemon at libre-soc.org bugzilla-daemon at libre-soc.org
Sun May 2 00:03:26 BST 2021


--- Comment #40 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Cesar Strauss from comment #38)
> I think this solution, which is commented out in dcache.py, is actually
> correct:
> comb += self.wb_in.stall.eq(self.wb_out.cyc & ~self.wb_in.ack)
> This interfaces a Classic slave with a Pipelined master (Wishbone B.4 5.2.1)
> The reason it doesn't work, as I see it, is because the SRAM is not handling
> the Classical cycle correctly.


> With both of the above changes, the DCache still works, but has a wait cycle
> in every transfer, due to limitations of the Classical cycle.

that's not a problem right now.

> On the other hand, we could keep it as is, but then we need to add a zeroed
> stall signal to the SRAM wishbone interface, since we are effectively in
> Pipeline mode. 

i would like to have some unit tests where the SRAM can randomly set the stall

> Anyway, I think it would be much better if we could have an SRAM with
> Pipelined mode, to avoid the extra wait states, and convert it to Classical
> when really needed.

yes.  this can be done by detecting if the  wb bus has a stall record attribute

  if hasattr(bus, "stall"):

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