[Libre-soc-bugs] [Bug 469] Create D-cache from microwatt dcache.vhdl

bugzilla-daemon at libre-soc.org bugzilla-daemon at libre-soc.org
Sat May 1 23:36:56 BST 2021


--- Comment #38 from Cesar Strauss <cestrauss at gmail.com> ---
I think this solution, which is commented out in dcache.py, is actually

comb += self.wb_in.stall.eq(self.wb_out.cyc & ~self.wb_in.ack)

This interfaces a Classic slave with a Pipelined master (Wishbone B.4 5.2.1)

The reason it doesn't work, as I see it, is because the SRAM is not handling
the Classical cycle correctly.

In sram.py, the following change is needed:

         # generate ack (no "pipeline" mode here)
         m.d.sync += self.bus.ack.eq(0)
-        with m.If(self.bus.cyc & self.bus.stb):
+        with m.If(self.bus.cyc & self.bus.stb & ~self.bus.ack):
             m.d.sync += self.bus.ack.eq(1)

Otherwise, in a Classic cycle, it will send an extra ack.

I will take a closer look at the SRAM test cases, in
src/soc/bus/test/test_sram_wishbone.py, to confirm it.

With both of the above changes, the DCache still works, but has a wait cycle in
every transfer, due to limitations of the Classical cycle.

On the other hand, we could keep it as is, but then we need to add a zeroed
stall signal to the SRAM wishbone interface, since we are effectively in
Pipeline mode. This is why the current DCache code works. But other masters,
that expect a Classical interface from the SRAM, may error out due to the extra

Anyway, I think it would be much better if we could have an SRAM with Pipelined
mode, to avoid the extra wait states, and convert it to Classical when really

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