[Libre-soc-bugs] [Bug 617] add SVP64 predication to TestIssuer
bugzilla-daemon at libre-soc.org
bugzilla-daemon at libre-soc.org
Sun Mar 21 13:12:58 GMT 2021
https://bugs.libre-soc.org/show_bug.cgi?id=617
--- Comment #8 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
cesar, my thoughts are that running the pipelines with zero inputs is not
useful, and that instead this is more useful and less... puzzling:
if (src_zeroing and ((1<<srcstep) & srcmask) == 0) or
(dest_zeroing and ((1<<dststep) & srcmask) == 0)):
result = 0
Condition_Register = EQzero
else:
RA = get_register_RA
RB = get_register_RB
result, Condition_Register = calc_operation(RA, RB)
http://lists.libre-soc.org/pipermail/libre-soc-dev/2021-March/002226.html
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