[Libre-soc-bugs] [Bug 605] Extend ECP5_FPGA wiki page with JTAG testing/boot procedure for Libre-SOC test chip

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=605

--- Comment #2 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
also this can be run (it uploads bytes 0x1 and 0x2 presently, needs to be given
a filename)
https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/debug/firmware_upload.py;hb=HEAD

it can be used to talk jtagremote protocol (via openocd) so that it actually
connects directly to the FPGA (or ASIC) and uploads firmware to it.

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