[Libre-soc-bugs] [Bug 605] Extend ECP5_FPGA wiki page with JTAG testing/boot procedure for Libre-SOC test chip

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=605

--- Comment #1 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Cole Poirier from comment #0)
> Once #517 JTAG STLINKv2 to FPGA connection guide wiki is complete:
> 
> * lkcl to outline Libre-SOC test chip boot via jtag procedure for testing on
> FPGA before the test ASIC is taped-out

in the README is the version for sim.py
https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/litex/florent/README.txt;h=2cab663850af1c530d852f948bf79e5795bb7e2a;hb=HEAD

the FPGA and ASIC variant is near-identical.

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