[Libre-soc-bugs] [Bug 656] add v3.0B BCD instructions to simulator

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=656

--- Comment #5 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Jacob Lifshay from comment #4)

> the code I wrote intentionally uses RA[4*i:4*i+3] since it's doing the add
> 4-bits at a time and manually propagating the carries rather than doing
> sequence of 60, 56, 52, 48, ... 8, and 4 bit adds and relying on the add to
> propagate carry implicitly. So, yes, 4*i+3 is correct here.
> 
> It uses a different algorithm than in the openpower spec.

then given that we are using the pseudocode as a recommendation for
changes to the OpenPOWER spec it is inadviseable to make unnecessary
changes regardless of "efficiency".

making such a change should go through the OPF ISA WG
where we pick it up from there once authorised and approved.

otherwise we have yet another discrepancy that requires yet more time
and yet more resources.

the reason why we had to make changes to mul, div and mod
pseudocode is because they were plain unuseable.

the existing pseudocode is useable.

if you want to propose a change to the Authorised ISA Spec through
the process soon to be established please feel free to do so, however
i would very much prefer that the LibreSOC pseudocode not contain
discrepancies that place a larger burden of time and energy on us
when the existing spec pseudocode generates the right values.

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