[Libre-soc-bugs] [Bug 656] add v3.0B BCD instructions to simulator

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=656

--- Comment #3 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Jacob Lifshay from comment #2)

> do i = 15 to 0
>     sum <- (0b0 || RA[4*i:4*i+3]) + (0b0 || RB[4*i:4*i+3]) + (0b0000 ||
> carry)

note 4*i:  >>>63<<<
not  4*i:  4*i+3

> > do i = 0 to 15
> >    dc[i] <- carry_out(RA[4*i:63] + RB[4*i:63])

therefore, each of the selections of RA and RB parts must be
expanded in length by 1 bit:

    temp <- (0b0 || RA[4*i:63]) + (0b0 || RB[4*i:63])

and because MSB0 order you take the bit numbered ZERO to get the MSB:

    dc[i] <- temp[0]

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