[Libre-soc-bugs] [Bug 251] Initial 3D MESA non-accelerated software-only driver is needed

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=251

--- Comment #66 from vivekvpandya <vivekvpandya at gmail.com> ---
(In reply to Jacob Lifshay from comment #64)
> (In reply to vivekvpandya from comment #60)
> > This particular path can get us started on LLVM side. I am thinking to
> > modify LLVM power-pc backend which will run a simple vectorizer pass (just
> > before Global ISEL)and create libre-soc specific LLVM intrinsics (can be
> > added with TD) and then updated Global Isel to generate libre-soc's textual
> > assembly for newly added llvm instrinsics.
> 
> we will eventually want to use llvm-ir's built-in support for vector types
> and use the common intrinsics/instructions rather than libre-soc-specific
> intrinsics, allowing waay more code to generate SV instructions without
> needing to be modified.

target specific intrinsics are common in LLVM (for example NVPTX) and in this
case it is just for one faze (CodeGen Prepare -> Global ISEL) 
Adding those intrinsics and doing a vectorization in codegen prepare. Again
this just makes codegen process easier. In other option I was thinking say an
add instruction is being fed with output of extract_vector (llvm instruction)
then in GlobalIsel we can match that pattern and generate code.

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