[Libre-soc-bugs] [Bug 588] add SVP64 to PowerDecoder2

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=588

--- Comment #3 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
commit b90ce1976820244dbd710d2c612933db7d5eece9 (HEAD -> master, origin/master)
Author: Luke Kenneth Casson Leighton <lkcl at lkcl.net>
Date:   Sat Jan 30 13:55:55 2021 +0000

    add SVP64 CR EXTRA field-extension, from 3-bit to 7-bit (plus isvec)
    in PowerDecoder2

added CR incoming register extending, CR outgoing is next.  test_issuer.py
is still working fine.

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