[Libre-soc-bugs] [Bug 588] add SVP64 to PowerDecoder2

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=588

Luke Kenneth Casson Leighton <lkcl at lkcl.net> changed:

           What    |Removed                     |Added
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                 CC|                            |cestrauss at gmail.com

--- Comment #2 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
commit 982a3a872f8969ab61e9f1c42194e1522be38de9 (HEAD -> master)
Author: Luke Kenneth Casson Leighton <lkcl at lkcl.net>
Date:   Sat Jan 30 00:36:22 2021 +0000

    add SVP64 EXTRA decoding to RB, RC and RT (out) in PowerDecode2
    DecodeOut2 will have to wait because it is more complex

Cesar i have the INT registers in the 3 input columns done, and one
output, but not the 2nd output yet (LDST-with-update), or the CRs.

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