[Libre-soc-bugs] [Bug 587] create setvl pseudocode, v3.0B fields, SVL-Form, and csv file

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=587

--- Comment #3 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Jacob Lifshay from comment #2)

> > wha-hey!
> 
> Neat!

yeh :)  the power_fields.py just reads
http://libre-soc.org/openpower/isatables/fields.txt

which is the sections 1.6 and 1.7 from the v3.0B spec in a machine-readable
format.

> Though I'd argue that ms shouldn't be a separate field since you want to set
> MVL every time you set VL.

ah no.  there's 4 combinations... actually 6 because RA can be zero
which indicates "use the immediate to set VL" and i can intuit/foresee
circumstances where MVL being set to a different value from VL is useful
or necessary.

it's not like RVV where you set one VL and the hardware decides, "yeah i'll
pick a different value".

there's unfortunately not enough room to have 2 sets of 7-bit immediates,
one to set VL the other to set MVL.

> Also, bits 22 and 23 need some documentation.

they're reserved, and in the page https://libre-soc.org/openpower/sv/setvl/
i also just added the descriptions to
http://libre-soc.org/openpower/isatables/fields.txt

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