[Libre-soc-bugs] [Bug 587] create setvl pseudocode, v3.0B fields, SVL-Form, and csv file

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=587

Jacob Lifshay <programmerjake at gmail.com> changed:

           What    |Removed                     |Added
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                 CC|                            |programmerjake at gmail.com

--- Comment #2 from Jacob Lifshay <programmerjake at gmail.com> ---
(In reply to Luke Kenneth Casson Leighton from comment #1)
> commit 23017a47970e7908664056261c3e2836a0257e44 (HEAD -> master,
> origin/master)
> Author: Luke Kenneth Casson Leighton <lkcl at lkcl.net>
> Date:   Fri Jan 29 11:56:35 2021 +0000
> 
>     start adding svp64 enums
> 
> commit c63a58b326a2b17d617b098261f217409c65402c
> Author: Luke Kenneth Casson Leighton <lkcl at lkcl.net>
> Date:   Fri Jan 29 12:11:17 2021 +0000
> 
>     add SV-Form for setvl instruction for Simple-V
> 
> 
> lkcl at fizzy:~/src/libresoc/soc/src/soc$ python3 decoder/power_fields.py
> 
> Form SVL
>         field ms BitRange([(0, 25)])
>         field RA BitRange([(0, 11), (1, 12), (2, 13), (3, 14), (4, 15)])
>         field Rc BitRange([(0, 31)])
>         field RT BitRange([(0, 6), (1, 7), (2, 8), (3, 9), (4, 10)])
>         field SVi BitRange([(0, 16), (1, 17), (2, 18), (3, 19), (4, 20), (5,
> 21)])
>         field vs BitRange([(0, 24)])
>         field XO BitRange([(0, 26), (1, 27), (2, 28), (3, 29), (4, 30)])
> 
> wha-hey!

Neat!

Though I'd argue that ms shouldn't be a separate field since you want to set
MVL every time you set VL.

Also, bits 22 and 23 need some documentation.

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