[Libre-soc-bugs] [Bug 583] Implement simple VL for-loop in nMigen for TestIssuer

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=583

--- Comment #14 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Luke Kenneth Casson Leighton from comment #11)
> https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/regfile/regfiles.py;
> h=e4ed80b18138c3d713538aaf9221ea40f2b2a24e;hb=refs/heads/master#l47
> 
> cesar if you can add SVSTATE to that list?  and also correct the comment, it
> should be 3 entries, whoops :)

done.  i might as well :)  not added into TestIssuer though.

commit 116c0f476db4984306c3547565fbe77dcc4cf800 (HEAD -> master)
Author: Luke Kenneth Casson Leighton <lkcl at lkcl.net>
Date:   Thu Jan 28 16:07:29 2021 +0000

    add SVSTATE to StateRegs
    (also fix comments)

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