[Libre-soc-bugs] [Bug 583] Implement simple VL for-loop in nMigen for TestIssuer

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=583

--- Comment #11 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/regfile/regfiles.py;h=e4ed80b18138c3d713538aaf9221ea40f2b2a24e;hb=refs/heads/master#l47

cesar if you can add SVSTATE to that list?  and also correct the comment, it
should be 3 entries, whoops :)

it is currently 4 long, DEC and TB are in fastregs, now.

PC=0
MSR=1
SVSTATE=2 

and, at lines 52/54 add an extra rd and extra wr port, call one w_sv the other
r_sv

then, here:
https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/simple/issuer.py;h=d662dff4c20e7904e6ca7cb3ae2ceaa6f03b6e06;hb=refs/heads/master#l110

ta-daaa, you can get those ports, w_sv and r_sv, and now you can read and write
SVSTATE.

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