[Libre-soc-bugs] [Bug 600] Fix MSB0 issues in the SVP64 Assembler, Simulator and Decoder

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=600

Luke Kenneth Casson Leighton <lkcl at lkcl.net> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
                 CC|                            |lkcl at lkcl.net

--- Comment #1 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
i really am getting fed up of MSB0.  it is going to be a major hindrance
in the v3.0B pseudocode with the proliferation of 63-i here, 31-i there.

i had forgotten to add this:

--- a/src/soc/decoder/isa/caller.py
+++ b/src/soc/decoder/isa/caller.py
@@ -686,6 +686,7 @@ class ISACaller:
         yield self.dec2.dec.bigendian.eq(self.bigendian)
         yield self.dec2.state.msr.eq(self.msr.value)
         yield self.dec2.state.pc.eq(pc)
+        yield self.dec2.state.svstate.eq(self.svstate.spr.value)

         # SVP64.  first, check if the opcode is EXT001, and SVP64 id bits set
         yield Settle()

which when i do so, because the bit-order is inverted the result is that
the register numbers get cranked up to 41 (the .v is mis-interpreted)

please bear in mind that ISACaller - and the SelectableInt class - actually
does MSB0 inversion automatically.  this is its job.

therefore technically speaking it is ISACaller that is "correct", and
PowerDecoder2 (or more specifically SVP64PrefixDecoder's interpretation
of the sv_rm field) that is likely to be wrong.

as in: although the bit-numbering has been inverted this may have also
inverted the order of the RM bits.

        rmfields = [6, 8] + list(range(10,32)) # SVP64 24-bit RM
        l = []
        for idx in rmfields:
            l.append(self.opcode_in[32-idx]) 
        with m.If(self.is_svp64_mode):
            comb += self.svp64_rm.eq(Cat(*l))

should be

        rmfields = [6, 8] + list(range(10,32)) # SVP64 24-bit RM
        l = []
        for idx in rmfields:
            l.append(self.opcode_in[32-idx]) 
  --->  l.reverse()
        with m.If(self.is_svp64_mode):
            comb += self.svp64_rm.eq(Cat(*l))

what's your thoughts there?

can you attach a patch (diff) here so i can take a look?

-- 
You are receiving this mail because:
You are on the CC list for the bug.