[Libre-soc-bugs] [Bug 600] New: Fix MSB0 issues in the SVP64 Assembler, Simulator and Decoder

bugzilla-daemon at libre-soc.org bugzilla-daemon at libre-soc.org
Tue Feb 16 14:22:55 GMT 2021


            Bug ID: 600
           Summary: Fix MSB0 issues in the SVP64 Assembler, Simulator and
           Product: Libre-SOC's first SoC
           Version: unspecified
          Hardware: PC
                OS: Linux
            Status: IN_PROGRESS
          Severity: enhancement
          Priority: ---
         Component: Source Code
          Assignee: cestrauss at gmail.com
          Reporter: cestrauss at gmail.com
                CC: libre-soc-bugs at lists.libre-soc.org
   NLnet milestone: ---

While investigating failures in test_issuer_svp64.py, I began noticing issues
in the decoder when extracting the SVP64 prefix fields, due to mistakes in MSB0
handling. Eventually, I found related issues in the assembler and simulator as

I think I managed to find and fix all such issues, locally. I did this by
checking, in GTKWave, the instruction memory against the expected hand
assembled instruction, and the decoded fields against the original instruction.
I kept fixing issues in the decoder, assembler and simulator, until
test_issuer_svp64.py passed.

Before I commit, I think maybe it would be better to first create a test case,
to confirm that the current version really has issues, and the fixes are not
introducing new bugs instead of fixing them.

The plan for this test case is to:

1) Have some list of SVP64 instructions (and a few non-SVP64 instructions as
2) Transform to v3.0B assembly, and compile
3) Check the binary result against the expected result, which was hand
assembled according to the SVP64 specification.
4) Pass the instruction to the decoder
5) Check decoded fields against the original instruction.

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