[Libre-soc-bugs] [Bug 583] Implement simple VL for-loop in nMigen for TestIssuer

bugzilla-daemon at libre-soc.org bugzilla-daemon at libre-soc.org
Fri Feb 12 17:57:43 GMT 2021


--- Comment #29 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
Cesar here's where in ISACaller, after decoding (all done already by
PowerDecoder2, now), the srcstep is added on:


you can see further down the write version.  then, even further down,
the "loop" which exits when SVSTATE.srcstep == VL-1

however the equivalent location - and i must apologise for this - is
handled by regspec_decode_read() and regspec_decode_write():


that's actually called here, get_byregfiles():

which returns a dictionary of tuples *kine 516), which in turn gets used by
connect_read/write_ports(), which in turn calls connect_read/write_port()

that tuple is unpacked here:

(also at line 260 for connect_readport)

now, *at the moment* it's relatively straightforward: regspec_decode_read/write
could in theory be modified to return a Mux() based on is_vec being set.

     Mux(e.read1_isvec, e.svstate.srcstep + e.read1_data, e.read1_data)

something like that

for elwidth overrides that's going to be a *lot* more complex... but for
now, that Mux should "do the trick"

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