[Libre-soc-bugs] [Bug 755] add grev instruction (OP_GREV)

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=755

--- Comment #18 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
i did a quick check (python3 nmutil/lut.py; yosys; synth; ltp) and this gives:

* 2048 cells for a 64-bit LUT3
* longest path 7

that means that a 6-layer 64-bit g-tern-log is going to be absolutely
massive: 13,000 cells (which are average... what... 5 gates each?)
and a path length of almost 50.  that will almost certainly have to
be at least a 3-stage pipeline.

the question is, then: is it worth it?  for the sheer awesome flexibility
it has - the number of options that can be covered - i'd say hell yes,
if it wasn't for the fact that it's 65 *thousand* gates - four times
larger than a 64-bit multiplier and three times larger than an IEEE754 FP
multiply.

which then begs the question: how can it be justified? what algorithms
could it cover that would justify its inclusion?

and: would a 32-bit variant be sufficient? a 32-bit variant would cut
the gate count to around.... 20,000?

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