[Libre-soc-bugs] [Bug 755] add grev instruction (OP_GREV)

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=755

--- Comment #15 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Jacob Lifshay from comment #14)

> > string.ascii_lowercase[:-length].rjust(fixedlen, "0")
> 
> that only works for the msb_first is False case. when msb_first is True, it
> produces names like 0buvwx00, which the above code doesn't do.

this should solve that:
s = reversed(string.ascii_lowercase[:-fixedlen]) if msb else
string.ascii_lowercase
return s.rjust(....)

(In reply to Jacob Lifshay from comment #13)
> (In reply to Luke Kenneth Casson Leighton from comment #12)
> > also can you put the rtlil creator back in, they are really useful
> 
> they're there, i added automatic rtlil writing to the do_sim function, so
> rtlil is written by every unit test.

yes, i know, and that is not the point.  i add rtlil outputting to
every module i write and both i and other people find it useful.
we are not interested in wasting time hunting for a unit test,
another file, or in wasting time waiting for that test to run, or
wasting even more time hunting through a bunch of unnecessary crud
looking for something that is unclear if it is even related to
the module.

please put it back.

-- 
You are receiving this mail because:
You are on the CC list for the bug.