[Libre-soc-bugs] [Bug 737] in-order single-issue Power ISA 3.0 core

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=737

--- Comment #32 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
i have this split out now, separate file
https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/simple/inorder.py;hb=HEAD

the goal here is to remove every FSM, or, more to the point, make every FSM
only one entry (one state).

an intermediary phase is to make every FSM two-state only:
one input ready/valid reader, one output ready/valid writer.

a Decode FSM (Decode stage) is currently missing, this should
involve pdecode2 and nothing else.  (oh except for state,
containing pc msr svstate i.e. CoreInput.

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