[Libre-soc-bugs] [Bug 755] add grev

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=755

--- Comment #2 from Jacob Lifshay <programmerjake at gmail.com> ---
(In reply to Luke Kenneth Casson Leighton from comment #1)
> commit 7aed55e3538fb39327bf4946843292d128d29abc (HEAD -> master,
> origin/master, origin/HEAD)
> Author: Luke Kenneth Casson Leighton <lkcl at lkcl.net>
> Date:   Sat Dec 11 15:29:09 2021 +0000
> 
>     add some comments (locations for comments to be added)
> 
> i took a quick look, one thing: i think you'll probably find this works:
> 
> 
>         # start with input as first layer
>         step_i = self.input
> 
>         for i in range(self.log2_width):
>             step_o = Signal(self.width, name=f"step{i}")

I specifically have the intermediate signals exposed because I want to have the
tests be able to access them to assert they have the correct values.

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